----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:20:04 03/30/2012 
-- Design Name: 
-- Module Name:    regFile - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity regFile is
    Port ( a1 : in  STD_LOGIC_VECTOR (2 downto 0);
           a2 : in  STD_LOGIC_VECTOR (2 downto 0);
           a3 : in  STD_LOGIC_VECTOR (2 downto 0);
           w : in  STD_LOGIC_VECTOR (7 downto 0);
           is_rw : in  STD_LOGIC;
           r1 : out  STD_LOGIC_VECTOR (7 downto 0);
           r2 : out  STD_LOGIC_VECTOR (7 downto 0);
           clk : in  STD_LOGIC);
end regFile;

architecture Behavioral of regFile is

type reg_box is array (0 to 7) of std_logic_vector (7 downto 0);
signal reg_file: reg_box := ((others => (others => '0' ))) ;
-- se inicializa todo a cero y asi la posicion 0 del 
--registro siempre estara a cero. Pues esa posicion no puede 
--ser escrita

begin

	process(a3,clk,is_rw)
	begin
		if rising_edge (clk) then
			if (is_rw = '0' and a3 /= "000" ) then
				reg_file(conv_integer(a3)) <= w;--escritura

			 
			end if;
		end if;
		
		end process;
				--lectura
				r1 <= reg_file(conv_integer(a1));
				r2 <= reg_file (conv_integer(a2));
end Behavioral;

